The advent of system-on-chip (SoC) design is driven by the maturity of integration technology and economical incentives. The integration of macros and intellectual properties (IPs) on the same chip not only results in better performance, but also lower packaging cost. However, SoC still faces many difficult technological challenges such as an effective test and design verification methodology. In addition, SoC can only integrate and fabricate macros using similar technology in order to ensure high yield and low cost. For example, NVRAM requires a floating gate process, which is not compatible with DRAM with deep trenches. It is even more difficult to incorporate desirable macros such as a high speed I/O macro built with SiGe circuits, micro-electro-mechanical systems (MEMS), sensors, or magnetic random access memory (MRAM) macros, on an SoC. Furthermore, SoC is limited by the overall chip size, as bigger chips usually result in lower yield and may require more redundant elements.